1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a thin film transistor and a method for fabricating the same.
2. Discussion of the Related Art
A thin film transistor (TFT) has been used instead of a load resistor or CMOS load transistor of an SRAM of more than 1M class. It is also used as a switching device which transforms picture data signals for pixel areas in a liquid display device. Particularly, in an SRAM cell using a PMOS TFT as a load transistor, the off-current of a PMOS can be reduced and the on-current of the PMOS can be increased, thereby reducing the power consumption and enhancing the memory performance.
An offset region significantly contributes stable performance to an SRAM cell, for example. Accordingly, the structure and the method of forming the offset region are important in the manufacture of semiconductor devices having offset regions.
A conventional TFT and a method for fabricating the same will be described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view of a conventional TFT, which includes an insulating layer 11, a gate electrode 13, a gate insulating layer 15, source and drain regions S/D, an offset region I, and a channel region II.
The gate electrode 13 is formed on a predetermined area of the insulating layer 11. The gate insulating layer 15 is formed on the insulating layer 11 including the gate electrode 13. The source region S is formed on the gate insulating layer 15 to overlap an edge of the gate electrode 13. The drain electrode D is formed on the gate insulating layer 15 apart from the gate electrode 13. The channel region II is defined from the end of the source region S formed over the gate electrode 13 to one end of the gate electrode 13. The offset region I is defined from the end of the gate electrode 13 to the end of the drain region D.
FIGS. 2A to 2E are cross-sectional views showing process steps of a conventional method for fabricating a TFT.
Referring to FIG. 2A, a first polysilicon layer 12 is formed on an insulating layer 11. A photoresist film (not shown) is coated on the first polysilicon layer 12 and patterned by an exposure and development process to form a gate pattern of the photoresist film.
Subsequently, using the gate pattern as a mask, the first polysilicon layer 12 is selectively etched to form a gate electrode 13, as shown in FIG. 2B.
Next, a gate insulating layer 15 is deposited on the insulating layer 11 including the gate electrode 13, as shown in FIG. 2C. Then, a second polysilicon layer 17 is formed on the gate insulating layer 15. The second polysilicon layer 17 is used as source and drain regions S/D as well as channel region II and offset region I.
Thereafter, as shown in FIG. 2D, a photoresist film is coated on the second polysilicon layer 17 and patterned by an exposure and development process to form a photoresist pattern 19 for a channel region and an offset region. Using the photoresist pattern 19 as a mask, impurity ions are implanted into the second polysilicon layer 17, thereby forming source and drain regions S and D.
Subsequently, the photoresist patter 19 is removed as shown in FIG. 2E to complete the conventional method for fabricating a TFT. Here, the offset region I is a portion of the second polysilicon layer 17 between the drain region D and the gate electrode 13, and the channel region II is a portion of the second polysilicon layer 17 that corresponds to the gate electrode 13.
Such a conventional TFT has the following problem. Processes using masks are required to form the channel region and the offset regions. It is generally difficult to perform mask alignment and associated photolithography precisely. Offset regions cannot be formed precisely with such an unstable process of mask alignment. This causes instability of the resultant cells.